1. Field of the Invention
The present invention relates to an insulated gate control thyristor which can be turned on and off by means of a control voltage applied to the gate thereof.
2. Description of the Prior Art
As a thyristor that can be turned off by the gate voltage, GTO (Gate Turn-Off) thyristors are well-known. The GTOs, however, have a low gate input impedance, and hence, require a considerable amount of gate current to turn off. For this reason, by utilizing a high input impedance insulated gate like that of a MOS structure, and by employing the semiconductor integrated circuit technique, various attempts have been made to fabricate thyristors that can turn off a large amount of current and have a relatively high withstanding voltage. This type of thyristor is known as an MCT (MOS Controlled Thyristor).
A typical conventional MCT will be described with reference to FIGS. 1A and 1B. FIG. 1A is a cross-sectional view showing a structure of an MCT unit, and FIG. 1B is a circuit diagram illustrating an equivalent circuit of the MCT unit.
A wafer or a semiconductor body 10 for the MCT is usually formed by growing an n-type epitaxial layer (a base region) 12 on a p-type substrate (an anode region) 11. On the surface of the body 10, a very thin insulating layer 13 such as a gate oxide film is formed, and then, gates 20 made of polysilicon or the like are formed in such a manner that the gates are in parallel with a narrow window W extending in the direction normal to the sheet of FIG. 1A. After that, a p-type emitter layer 30 of a considerable depth, an n-type cathode layer 40, and shallow p-type source layers 80 are embedded into the epitaxial layer (base region) 12, as shown in FIG. 1A, by the ion implantation of impurities from the surface the epitaxial layer 12 using portions of the gates 20 as masks, followed by the annealing of the impurities. Subsequently, insulating films 14 covering the gates 20 are formed on top of the gates, and then, an electrode film 15 making ohmic contact with the cathode layer 40 as well as with the source layer 80 is formed in the window W. In addition, an electrode film 17 making ohmic contact with the substrate 11 is formed on the bottom of the semiconductor body 10.
Thus, a four layer pnpn structure, which characterizes the thyristor and comprises the p-type substrate 11, the epitaxial layer 12, the p-type emitter layer 30, and the cathode layer 40, is formed on the semiconductor body 10. Further, an anode terminal A is led from the electrode film 17 making ohmic contact with the substrate 11, a cathode terminal C is led from the electrode film 15 shortcircuiting the cathode layer 40 and the source layer 80 on their surfaces, and a gate terminal G is led from the gate 20 at a cross-section different from that of FIG. 1A. Incidentally, the substrate 11 serves as the p-type anode region in the thyristor structure. In general, the unit structure shown in FIG. 1A are repeated a number of times in the lateral direction so as to form one MCT.
As shown in an equivalent circuit of FIG. 1B, the MCT includes a pnp transistor 61 and an npn transistor 62. The pnp transistor 61 comprises the n-type epitaxial layer 12 functioning as the base between the anode region 11 and the emitter region 30, whereas the npn transistor 62 comprises the p-type emitter layer 30 functioning as the base between the n-type epitaxial layer 12 and the cathode layer 40. In addition, as shown in FIG. 1B, the MCT includes an n-channel MOS transistor 71 connected in parallel with the npn transistor 62, and a p-channel MOS transistor 72 formed between the p-type emitter layer 30 and the cathode terminal C. More specifically, as seen in FIG. 2 which is a partially enlarged cross-sectional view in the vicinity of the gate 20, the n-channel MOS transistor 71 is formed between the n-type epitaxial layer 12 and the cathode layer 40 in such a way that its channel CH1 is formed in the surface of the p-type emitter layer 30 under the gate 20, and the p-channel MOS transistor 72 is formed between the p-type emitter layer 30 and the source layer 80 in such a way that its channel CH2 is formed in the surface of the n-type cathode layer 40 under the gate 20.
The MCT is turned on as follows by supplying the gate terminal G with a control voltage positive with regard to the cathode terminal C. First, the control voltage conducts the MOS transistor 71, and then the pnp transistor 61 is turned on by its base current induced by the conductive MOS transistor 71. This in turn induces the base current of the transistor 62, which turns on the npn transistor 62, thereby turning on the MCT. At the start of the turn-on action, the epitaxial layer 12 serves as the base region of the transistor 61 into which the base current is injected. Although it is necessary to inject electrons into the base region 12 through the channel CH1 of the MOS transistor 71 to turn on the MCT, once the MCT has turned on, the MCT maintains its on state even after the control voltage applied to the gate 20 has been removed. This is because a current i, which flows from the anode terminal A to the cathode terminal C across the anode region 11, epitaxial layer 12, emitter layer 30 and the cathode layer 40 as shown in FIG. 2, supplies both transistors 61 and 62 with their base currents so as to maintain their on state.
The MCT is turned off as follows by a negative control voltage applied to the gate terminal G. The negative control voltage conducts the MOS transistor 72, which divides the current i flowing from the transistor 61 to the transistor 62 so as to induce a current ib flowing through the channel CH2 of the MOS transistor 12 as shown in FIGS. 1B and 2. This results in a shortage of the base current of the transistor 62, thereby turning off the MCT.
Prior art insulated gate control thyristors, which includes the above-described MCT as a typical example, can be turned on and off by temporarily supplying their high input impedance gates with positive or negative control voltages. In addition, they have high withstanding voltages of several hundred Volts and large current capacities of several tens of Amperes, and since they are thyristors, they have small on-state voltage drops on the order of magnitude of those of diodes. The conventional insulated gate control thyristors, however, have problems in that the turn-off characteristics are insufficient, and the diffusion process of the semiconductor layers is not easy. These problems are explained below.
First, the turn-off problem will be explained. To turn off the MCT, the current i injected into the emitter layer 30, must be extracted from the cathode terminal C by way of the channel CH2 of the MOS transistor 72 and the cathode layer 80 by conducting the MOS transistor 72, as shown in FIG. 2. In this case, the current ib divided and extracted is only a part of the current i. Accordingly, if the divided ratio is insufficient, and hence, the recovery of the junction between the emitter layer 30 and the cathode layer 40 is delayed, the turn-off time is lengthened, or the turn-off cannot be achieved in the worst case. Furthermore, since an inner resistance 31 of the emitter layer 30 is interposed on the way of the divided current ib, as shown in FIG. 2, the potential under the electrode film 15 for the cathode terminal C becomes higher than the potential in the close proximity to the channel CH2. This induces a junction voltage between the emitter layer 30 and the cathode layer 40, and hence, holes are injected into the cathode layer 40 from the emitter layer 30 owing to the junction voltage. In response to this, electrons are reinjected from the cathode layer 40 into the emitter layer 30, which constitutes the base current of the transistor 62 as shown in FIG. 1B. This makes it difficult to turn off the transistor 62, and hence, to turn off the thyristor.
In a fabrication aspect, the problem is that considerably deep diffusion of a semiconductor double layer is needed which is composed of two reversal conductivity type layers, the emitter layer 30 and the cathode layer 40. The diffusion depth of the emitter layer 30 and the cathode layer 40 must be precisely controlled because it directly relates to the lengths of the channels CH1 and CH2. Furthermore, the impurity concentrations of the emitter layer 30 and the cathode layer 40 must be approximately equal so that the threshold values of the MOS transistors 71 and 72 of FIG. 1B will agree. It is difficult, however, to match the impurity concentrations of the two layers of the reversal conductivity type double layer, and further, to precisely control the diffusion depth of the double layer in the wafer process, which results in variations of products.
Furthermore, the depth of the base region 12 of FIG. 1A determines the withstanding voltage of the transistor 61, and accordingly, that of the thyristor. This depth of the base region 12 must be increased by a considerable amount because the semiconductor double layer of the emitter layer 30 and the cathode layer 40 must be diffused into that region 12. The depth of the base region 12, however, greatly effects the characteristics of the thyristor: the switching speed decreases as the thickness of the base region 12 increases; and the on-state resistance of the thyristor increases in rough proportion to the thickness of the base region 12.